@inproceedings{Yeolekar:2012:SUD:2206781.2206862,
 author = {Yeolekar, Pranav and Shafik, Rishad A. and Mathew, Jimson and Pradhan, Dhiraj K. and Mohanty, Saraju P.},
 title = {STEP: a unified design methodology for secure test and IP core protection},
 booktitle = {Proceedings of the great lakes symposium on VLSI},
 series = {GLSVLSI '12},
 year = {2012},
 isbn = {978-1-4503-1244-8},
 location = {Salt Lake City, Utah, USA},
 pages = {333--338},
 numpages = {6},
 url = {http://doi.acm.org/10.1145/2206781.2206862},
 doi = {10.1145/2206781.2206862},
 acmid = {2206862},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {intellectual property core, secure test, security and protection},
}