Source code of
the TERO-PUF implementation on SRAM FPGA
In this page, the source codes of the
implementations of the TERO-PUF are available:
- Sources codes for
Xilinx Spartan 6 FPGAs (XC6SLX16-2FTG256C) : files
- Sources codes for Altera Cyclone V FPGAs (EP5CEBA4F17C8N) :
files
- The following document explain technical details about the
two implementations and provides explainations on the system
used
to implement the TERO-PUF : readme.pdf
The
TERO-PUF has been implemented on FPGAs using the Evarist III
system which is a modular hardware system. An overview of the system is
provided in the readme file. In addition, the communication protocol
used to send challenges and receive data from the PUF is also presented
in this file. More information about the Evariste III system are
provided here.