Home

Publications

Salware bibliography

Bloc cipher
implementations


TERO-PUF
implementation


Contacts:
mail to Lilian Bossuet

Lilian Bossuet's personnal web page

Source code of the TERO-PUF implementation on SRAM FPGA

In this page, the source codes of the implementations of the TERO-PUF are available:
The TERO-PUF has been implemented on FPGAs using the Evarist III system which is a modular hardware system. An overview of the system is provided in the readme file. In addition, the communication protocol used to send challenges and receive data from the PUF is also presented in this file. More information about the Evariste III system are provided here.